FIELD OF THE INVENTION
The invention relates to a column redundance circuit configuration for a memory having a memory blocks with memory cells disposed in x lines and y columns, redundant memory cells being disposed in b lines and c columns, a column decoder, c redundant column decoders, each column decoder being assigned to a respective one of the c redundant columns of each memory block, and d encoding elements.
One such configuration is described in IEEE Journal of Solid State Circuits, Vol. 26, No. 1, January 1991, pp. 12 ff., for example.
The reduction in raster dimensions with each new memory generation increases the vulnerability to defects in the cell field. Cost-effective production therefore requires devices on the memory with which such defects can be repaired. As a rule, supplementary cells are provided, which are used instead of the defective cells by means of programmable encoding elements.
In larger-capacity memories, the memory cells are subdivided into a plurality of blocks. Due to the matrix-like configuration of the memory cells, the supplementary cells must also be disposed in rows and columns. Such redundant lines are generally formed at the edge of the cell fields. They are each selected by a programmable element in connection with the addresses being applied.
The programmable elements may be laser-separable fuse blocks, for instance. Typically, each fuse block has one or more redundant lines fixedly assigned to it. If the repair capability is to be increased, then the number of redundant lines must be increased, and therefore the number of fuse blocks as well. The space required for that kind of increase in redundance is substantial and can lead to a reduction of the number of pieces per wafer. In present memory generations, the surface area required for the fuse blocks together with their trigger circuits is approximately as large as the surface area occupied by the redundant memory cells. On one hand, statistics for redundance utilization, for instance in a 4 MB memory, show that on average only half of the fuse blocks are employed for repair. On the other hand, defect analysis has shown that doubling the redundance makes an up to 20% higher yield possible. That shows that in the structure of redundance architecture up to now, a substantial proportion of memories cannot be repaired, even though in principle enough programmable encoding elements are available.
If the repair capability is to be increased even further, then it would be advantageous for reasons of space if only the number of redundant lines had to be increased, and if better utilization of existing fuse blocks could be achieved by suitable switching.
If column redundance is expanded, the increase in power consumption represents a further problem. In contrast to triggering the row redundance, which is used only at the beginning of a cycle, triggering of the column redundance must be operationally ready over the entire active cycle. Since triggering circuits with dynamic logic and quadrature-axis current components have previously been used therefor, expanding the column redundance at the same time also means increasing the power consumption.